1. Field of the Invention
The present invention relates to a semiconductor device, and more particularly, to a cylindrical-structure transistor including a channel formed perpendicular to a substrate.
2. Description of the Related Art
Compact and large-capacity non-volatile semiconductor memory devices have been increasingly required. NAND flash memories draw attention to the possibility of higher integration and a larger capacity.
For higher integration and a larger capacity of the NAND flash memories, a smaller design rule is necessary. A smaller design rule requires further microfabrication of wiring patterns or the like. Because further microfabrication of the wiring patterns or the like requires highly advanced manufacturing technologies, it becomes more difficult to reduce the design rule.
For the purpose of more highly integrated memory devices, a large number of semiconductor memory devices have recently been proposed that include three-dimensionally disposed memory cells (see, for example, JP 2003-078044, and Masuoka et al., “Novel Ultrahigh-Density Flash Memory With a Stacked-Surrounding Gate Transistor (S-SGT) Structured Cell,” IEEE TRANSACTIONS ON ELECTRON DEVICES, VOL. 50, NO. 4, pp. 945-951, April 2003).
Many of the conventional semiconductor memory devices including three-dimensionally disposed memory cells requires, for each layer of the memory cell portion, a plurality of photo-etching processes (i.e., patterning processes including a lithography process using a photoresist and a fabrication process such as etching). A photo-etching process with a minimum line width of the design rule is referred here to as a “critical photo-etching process.” A photo-etching process with a line width larger than the minimum line width of the design rule is referred here to as a “rough photo-etching process.” The conventional semiconductor memory device including three-dimensionally disposed memory cells requires three or more critical photo-etching processes for each layer of the memory cell portion. Because many of the conventional semiconductor memory devices simply laminate memory cells, cost increase due to the three-dimensional structure is inevitable.
One of the conventional semiconductor memory devices including three-dimensionally disposed memory cells is a semiconductor memory device that includes a cylindrical-structure transistor (SGT: Surrounding Gate Transistor). See for example, JP 2003-078044.
The cylindrical-structure transistor (SGT) has following advantages. The transistor channel is formed perpendicular to a substrate surface, and so the channel length may be increased without an increase of the chip area. The channel is also generally formed in the film thickness direction that has high process controllability, and so the gate length may be controlled more precisely.
Although the gate length may be controlled more precisely, the profiles of the source/drain diffusion layers tend to be more difficult to be controlled, as compared to the planar transistors.
Proposed processes for forming the source/drain impurity layers include:
(a1): impurity diffusion in the direction normal to the substrate from impurity diffusion regions formed in the silicon substrate surface;
(a2) ion implantation from above the substrate; and
(a3) impurity diffusion in the lateral direction from an interlayer dielectric film with impurities previously doped therein.
Since the processes a1 and a3 are easily affected by thermal processing, they have a difficulty in optimizing the gate overlap amount and the LDD structure. In the process a2, the formation of the source/drain impurity regions at deep points on the silicon substrate side should use a high-acceleration ion implantation. It thus tends to take a longer process time to form therein an impurity-diffusion region with a relatively high concentration, resulting in a lower manufacturing throughput.